The present disclosure relates in general to semiconductor devices and their manufacture. More specifically, the present disclosure relates to the fabrication of a uniform leakage current stopper to counter under channel leakage currents in a fin-type field effect transistor (FinFET) device.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
One particularly advantageous type of MOSFET is known generally as a fin-type field effect transistor (FinFET). A three-dimensional view of an exemplary FinFET 100 is shown in FIG. 1A. The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional field effect transistor. FinFET 100 includes a semiconductor substrate 102, a shallow trench isolation (STI) layer 104, a fin 106 and a gate 114, configured and arranged as shown. Fin 106 includes a source region 108, a drain region 110 and a channel region 112, wherein gate 114 extends over the top and sides of channel region 112. For ease of illustration, a single fin is shown in FIG. 1A. In practice, FinFET devices are fabricated having multiple fins formed on STI 104 and substrate 102. Substrate 102 may be silicon, and STI 104 may be an oxide (e.g., SiO2). Fin 106 may be silicon that has been enriched to a desired concentration level of germanium. Gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1A). In contrast to a planar MOSFET, however, source 108, drain 110 and channel 112 are built as a three-dimensional bar on top of STI layer 104 and semiconductor substrate 102. The three-dimensional bar is the aforementioned “fin 106,” which serves as the body of the device. The gate electrode is then wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. The source and drain regions are the portions of the fin on either side of the channel that are not under the gate electrode. The dimensions of the fin establish the effective channel length for the transistor.
FinFETs have been made successfully for mass manufacturing on bulk and silicon-on-insulator wafers. The demand for higher levels of integration includes a push to reduce transistor channel length. Several factors limit the ability to reduce transistor channel lengths past a certain level. For example, if the channel length is reduced such that it is shorter than an operational limit, undesirable results such as short channel effects and punch-through may occur. In general, punch-through occurs when, during an off state of the transistor, an under channel pathway extending through the substrate underneath the gate-controlled portion of the channel region allows leakage currents to pass from the source to the drain.
When choosing the bulk option to manufacture FinFETs, additional process steps are needed for substrate leakage suppression. Typically, a high-dose punch-through stop implant at the base of the fins is needed to create dopant junction isolation. This is especially true for pFET, because it is preferable to recess the fin deeper (beyond the gate/isolation boundary) to achieve both uniform junction formation from the top portion of the fin to the bottom portion of the fin, as well as enhanced embedded silicon germanium (eSiGe) stress coupling. Heavy substrate doping has been used to stop punch-through (i.e., leakage currents) from occurring between the source and drain. However, precise control of the doping profile to prevent its up-diffusion into the channel has been a challenging task, especially in the context of continuously shrinking device dimensions.